Robust NMOS and other ESD protection are crucial to obtain high levels of ESD robustness in CMOS technologies. In processes with the option of local blocking of silicide, ballasting resistance is introduced to ensure equal current spreading and uniform multi-finger triggering.
In order to achieve adequate ESD protection levels with high failure thresholds and good clamping capabilities, sufficient device width must be provided. Therefore, multi-finger MOS structures have been implemented for ESD protection. Furthermore, advanced CMOS technologies require high numbers of fingers, since decreasing pad pitch and minimum active area width might be largely restricted by design limitations.
A major concern with regard to multi-finger devices under ESD stress is the possibility of non-uniform triggering of the fingers. In order to ensure uniform turn-on of multi-finger structures, the voltage value at the second finger breakdown Vt2 must exceed the triggering voltage Vt1 of the parasitic BJT transistor, i.e. the voltage at the onset of snapback. In order to avoid damaging an initially triggered finger from a high current load, the adjacent fingers must also be switched on into the low resistive ESD conduction state (i.e. snapback). To achieve a homogeneity condition Vt1<Vt2, either the initial triggering voltage Vt1 must be reduced or the second breakdown voltage Vt2 must be increased.
Complications arise, for example, in standard I/O library cells, where the multi-finger MOS device is formed as a split device. In particular, the multi-finger device is formed as a split device where a first portion of the fingers is actively used by circuitry of an integrated circuit (IC) for functional purposes (i.e., the driver), and a second portion of the fingers is utilized only for ESD protection (i.e., the dummy ESD fingers). The multi-finger device can be configured for several drive strengths by including or excluding a particular number of fingers from being driven at their respective gates by a pre-driver. That is, during normal circuit operation the active fingers are controlled by the pre-driver, while the non-active dummy ESD fingers are not utilized. In this latter instance, the gates of the unused driver fingers are typically grounded, either directly or indirectly, through a resistance. During an ESD event, trigger competition between the actively used (driver fingers) and unused fingers (dummy ESD fingers) may cause non-uniform turn-on of the normally active and non-active fingers. Specifically, the driver fingers may trigger prior to the dummy ESD fingers (i.e., non-uniform turn-on of all the fingers), which may result in failure of the MOS device and damage of the IC. As such, only a part of the total device carries ESD current, while the remainder of the device does not contribute to the current flow and remains unused.
Further problems arise for drivers or other I/O circuitry, which are configured to be over-voltage tolerant (OVT). That is, the voltage that is applied to the I/O circuitry may be higher than the supply voltage (e.g. VDD). In many over-voltage cases, a single NMOS driver may be susceptible to hot carrier injection because the applied voltage exceeds the normally specified maximum voltage between drain and gate.
One method to overcome hot carrier injection concerns is to use a cascoded output driver. That is, two NMOS devices (transistors) are connected in series between an I/O pad of the IC and ground. The serially connected cascoded NMOS transistors form the output driver. The gates of the active cascoded NMOS transistor fingers, whose source is coupled to ground, are driven by the pre-driver.
Alternatively, the gates of the non-active (dummy ESD fingers) cascoded NMOS transistor fingers are tied to ground. Furthermore, the gates of the active and non-active NMOS transistor fingers are tied to a supply line (e.g., VDD) in a normally turned on condition, while drains are coupled to the I/O pad. In this manner, neither of the cascoded NMOS transistor's drain-gate potential can increase enough to cause a hot-carrier concern.
However, during an ESD event, the cascoded devices are difficult to trigger due to the longer base length of the parasitic NPN transistor. As such, the Vt1 value increases, while the Vt2 value remains substantially constant, thereby causing additional non-uniform triggering problems of the cascoded NMOS driver. Again, the issue of trigger competition may cause only a part of the transistor fingers to trigger, thereby causing premature failure. As such, there is a need in the art to provide an ESD protection device with simultaneous and distributed self-biasing for multi-finger turn-on.